1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and, more particularly, to a non-volatile semiconductor memory device that erases data stored in a memory cell using a Fowler-Nordheim (FN) tunnel current.
2. Description of the Related Art
A great deal of attention has been paid to non-volatile semiconductor memories, such as a Ferro-electric Random Access Memory, EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). The EPROM and EEPROM have a plurality of memory cells each including a floating gate for storing a charge and a control gate for detecting a change in the threshold voltage in accordance with the quantity of charge stored in the floating gate. Therefore, data is stored using these types of memory cells. The EEPROM can erase data of the entire array of memory cells. The EEPROM includes a flash EEPROM, which has the memory cell array separated into a plurality of blocks and can thus selectively erase data block by block. The flash EEPROM has the following advantages:
(1) Non-volatile property for stored data, PA1 (2) Low power consumption, PA1 (3) Electrically rewritable (rewritable on board), and PA1 (4) Low cost.
Therefore, this flash EEPROM is widely applicable as a memory for storing programs or data in electronic devices, such as portable telephones and portable information terminals. There are two types of flash EEPROMs at present: split gate type and stacked gate type.
U.S. Pat. No. 5,202,850 and International Patent Publication WO92/18980 disclose a split gate flash EEPROM. FIG. 1 is a schematic cross-sectional view of a split gate memory cell 102 provided in a split gate type flash EEPROM of U.S. Pat. No. 5,202,850. The split gate memory cell 201 has an N-type source S and N-type drain D, both defined on a P-type single crystalline silicon substrate 102, a floating gate FG provided on a first insulator film 103 over a channel CH between the source S and drain D, and a control gate CG located a second insulator film 104 over the floating gate FG. A part of the control gate CG is arranged as a select gate 105 on the channel CH via the first insulator film 103. International Patent Publication WO92/18980 discloses a flash EEPROM in which the source S of the split gate memory cell 101 is identified as a "drain" and the drain D is identified as a "source".
FIG. 2 is a schematic cross-sectional view showing a conventional stacked gate NOR type memory cell 201. The stacked gate memory cell 201 has a source S and a drain D, both having an N-type conductivity and defined on a single crystalline silicon substrate 202 having a P-type conductivity, a floating gate FG located on a first insulator film 203 over a channel CH between the source S and the drain D, and a control gate CG arranged on a second insulator film 204 over the floating gate FG. The floating gate FG and the control gate CG are stacked without deviation from each other. Therefore, the source S and the drain D are defined symmetrically to the gates FG and CG and the channel CH.
In the erase mode of the split gate memory cells in FIG. 1, electrons in the floating gate electrode FG are drained toward the control gate electrode CG as indicated by the arrow A, erasing data stored in the memory cell 101. In the erase mode of the stacked gate NOR type memory cells in FIG. 2, electrons in the floating gate electrode FG are drained toward the drain region D as indicated by the arrow B, erasing data stored in the memory cell 201. As the electrons pass the silicon oxide film 104 or 203, large stress is applied to the silicon oxide film 104 or 203. Therefore, repeated writing and erasure increase the stress that is applied to the silicon oxide film 104 or 203, thus forming an electron trap in the silicon oxide film 104 or 203. This electron trap interferes with the movement of the electrons to the control gate electrode CG or the drain region D from the floating gate electrode FG. As the number of writings and the number of erasures (i.e., the number of rewritings) increase, therefore, it becomes impossible to properly drain electrons from the floating gate electrode FG.
In the read mode of each memory cell 101 or 201, as shown in FIG. 3, the current (cell current) Iw, which flows into the memory cell 101 or 201 in a data written state, does not change with an increase in the number of data rewritings. On the contrary, the current (cell current) Ii, which flows into the memory cell 101 or 201 in a data erased state, decreases as the number of data rewritings increases in the read mode of each memory cell 101 or 201. As a result, the value of the cell current Ii approaches the value of the cell current Iw. When the cell current Ii drops further and becomes smaller than a predetermined cell current Ir1, it become impossible to determine from the cell current whether the memory cell 101 or 201 is in a written state or in an erased state. That is, data stored in the memory cell 101 or 201 cannot be read out. The predetermined cell current value Ir1 is determined by the characteristics of sense amplifiers in the flash EEPROM. This cell current value Ir1 represents the lower limit of the cell current Ii flowing in the memory cell 101 or 201 in the data erased state.
As apparent from the above, the operational life of the memory cells 101 or 201 is limited by the number of data rewritings. This means the operational life of the flash EEPROM provided with memory cell 101 or 201 is similarly limited.